Production of semiconductor integrated circuits and other microelectronic devices from semiconductor wafers requires formation of one or more metal layers on a wafer. These metal layers are used, for example, to electrically interconnect various devices of the integrated circuit. These metal layers may be, for example, nickel, tungsten, solder, and copper. These metals can be deposited using various different techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating.
Prior to the formation of metal interconnects, a barrier layer is formed in patterned structures such as, for example, vias, trenches or other features. The barrier layer is used to prevent movement of materials between the circuit patterns into an adjacent dielectric layer. The barrier layer is typically tantalum, or tantalum nitride, deposited into the vias and trenches by PVD processes. After the barrier layer is formed, a copper seed layer, for example, is deposited over the barrier layer and, thereafter, an electroplating process forms the copper interconnect layer.
However, it has been found that during the fabrication (e.g., PVD process) of the barrier layer, tantalum or tantalum nitride also deposits on the wafer. This forms a metal film on the entire wafer surface including at the edges and extreme edges or bevel of the wafer. This layer is very thin, typically in the range of 2 to 100 nanometers. It has also been found that the adhesion of the thin film to the wafer is not very reliable due to, at least, the concentration of the nitrogen (a mol percentage of less than 20%) to tantalum. It is also theorized that damage by semiconductor wafer processing steps, such as the damascence reactive ion etching (RIE) process, as well as from ion bombardment as a secondary result of the PVD process, causes damage to the near-silicon surface at the wafer edge. This damage then in turn promotes poor adhesion of dielectric layers that are deposited overtop the silicon wafer. The subsequent poor adhesion of the TaN layer, and exacerbated by its low nitrogen content, leads to subsequent flaking of the Tan and any material overtop the TaN barrier at the wafer edge and extreme edge. Due to the chemical composition of the TaN, this film has a tendency to flake off during subsequent processes of the integrated circuit.
This flaking, in turn, results in an increase in defect creation. More specifically, due to stresses imposed on the wafer in subsequent processes, the thin film of TaN flakes off, resulting in a significant increase in particle generation. This increase in particle generation will significantly reduce product yield and device reliability.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.